With multi-core system (also called chip-multi-processor (CMP)) having gradually become a main trend for current computer system and with the constant development of virtualization, the design of L2 cache develops accordingly. The typical structure of a multi-core system is shown in FIG. 1. In the multi-core system, each core on a processor has a private L1 cache (not shown in FIG. 1) for holding some data. Besides, multiple cores may share one L2 cache, and then a plurality of L2 caches 130A, 130B, 130C, and 130D may form a cache coherence system. In other words, the current computer system has a cache coherence mechanism. Under the control of a manager 140, the cache coherence mechanism is essentially used to help the system to maintain data coherence, which means if more than one backup of a data block is located in more than one L1 and L2 caches at the same time, the coherence mechanism may guarantee that the values of all backups at each time are completely identical.
The process of the cache coherence mechanism may be described as follows:
Firstly, for example, a core 1 on the L2 cache 130B intends to load a data block and searches the data block in its private L1 cache A (not shown). Then, if backup of the data block is found in the private L1 or L2 cache 130B, then the data loading process ends, and the coherence process will not be called. However, if backup of the data block is not found in the private L1 or L2 cache 130B, then the coherence process will be called. The request for the data block will be transmitted by the L2 cache 130B to all other L2 caches 130A, 130C, and 130D. Next, the L2 caches 130A, 130C, and 130D will search the requested data block in their own arrays. If one of the caches finds a backup, then the cache which finds the backup will issue a confirmation message to the L2 cache 130B. Meanwhile, the cache which finds the backup will remove its own data backup so as to guarantee that the values of the data block in all caches are identical. However, if none of other L2 caches 130A, 130C, and 130D finds the backup of the data block, then a memory will issue the data to the L2 cache 130B. All in all, the cache coherence mechanism aims to enabling data backups among all L2 caches to be completely identical, thereby achieving coherency of data.
Thus, in a current multi-core system having a cache coherence mechanism, upon occurrence of a request for data, it is required to access all L2 caches, which results in consuming considerable power. In fact, in most situations, a request for data cannot be found in other L2 caches than the L2 cache which issues out the data request, thus in the current system, the process of searching said data in all other L2 caches based on the request is totally unnecessary. Such searching process will waste about 30% to 40% of the power of L2 caches.
There are already some solutions to alleviate the above problems in the prior art. One solution thereof is based on a hash table. This solution uses a hash table to encode and record logical partition IDs (LPID) of all logical partitions running on L2 caches. When a data request is received, the LPID attached to the data request is extracted through a hash function and mapped to a value. The value then is compared with all entries recorded in the hash table. However, due to inherent substantive defects of the hash table, such filtration cannot realize an accurate mapping and has high false positives, thereby reducing power efficiency. Another solution is based on historical records of data access. This solution uses a historical record table for maintaining records of data access. However, the filtration ratio obtained through this solution depends on the size of the historical record table too much extent. The more the requests for filtration are, the larger should be the size of the table. Thus, it is easily seen that a large-sized historical record table per se will cost hardware module size and power consumption. Thus, in order to reduce power consumption, it is desirable to provide a system and method for reducing and even eliminating the above-mentioned unnecessary and vain process of searching L2 caches.